EDN

On-Chip Design Verification with Xilinx FPGAs

Xilinx Virtex-II Pro devices have redefined FPGAs. The Virtex-II Pro brings with it not only a denser and faster FPGA, but an IBM PPC 405 core and up to twenty four 3.125Gb/s high speed serial ...
EDN

Asynchronous circuits: better power by design

Managing the power consumption of ICs is an increasingly difficult challenge, because each new generation of portable device includes expanded features and demands longer battery lives.
Design-Reuse

Tiempo Unveils First Timing-Driven Design Flow for its Innovative Clockless Chip Design Technology

Grenoble, France – June 07, 2010 – Tiempo,SAS, a developer of innovative clockless technology for the design of low power integrated circuits (ICs), today announced its ability to support the use of ...
Nature

Asynchronous Processors and Low-Power Sensor Networks

Asynchronous processors, which function without a global clock, have emerged as a compelling alternative to traditional synchronous architectures. Their design relies on handshake protocols and local ...
Design-Reuse

Ultra Low Power Designs Using Asynchronous Design Techniques (Welcome to the World Without Clocks)

Wire delay is beginning to dominate gate delay in current CMOS technologies. According to Moore’s Law by 2016 CMOS feature size should be on the order of 22 nm with clock frequencies reaching around ...