EDN

Last-level cache has become a critical SoC design element

LLC, positioned between external memory and internal subsystems, stores frequently accessed data close to compute resources.
TweakTown

Leaked AMD Medusa Point 'Zen 6' 10-core test sample matches current generation equivalent at less than half the clock speed

These next-generation laptop processors are also reported to receive a bump across both CPU core counts and L3 cache configurations.
Forbes

AMD Turbocharges Ryzen 7 9800X3D With New 3D V-Cache Design

Information has leaked regarding AMD's new and highly anticipated Ryzen 9000X3D processors that could make then devastatingly quick and not just in games. Next generation 3D V-Cache will, according to ...
Design-Reuse

Modular Design Of Level-2 Cache For Flexible IP Configuration

The microprocessor-memory gap has been growing for over 30 years, and in that time caches have been crucial components in digital system design. All high-performance microprocessors are designed with ...
PC Gamer

AMD talks about its upcoming 3D V-Cache design at ISSCC

Those AMD boffins are doing some good work. When you purchase through links on our site, we may earn an affiliate commission. Here’s how it works. AMD has teased its 3D V-Cache technology for several ...
Design-Reuse

Co-Designed Cache Coherency Architecture for Embedded Multicore Systems

One of the key challenges in chip multi-processing is to provide a programming model that manages cache coherency in a transparent and efficient way. A large number of applications designed for ...
Electronic Design

AMD Takes EPYC Server CPUs to Another Level With 3D Cache

AMD is raising the bar in its battle against Intel in the data center with a new lineup of EPYC CPUs that use its 3D packaging technology to triple the L3 cache, giving them a significant hike in ...