SAN JOSE, Calif. — MIPS Technologies Inc. has launched DSP ASE, digital signal processing extension to the MIPS architecture. The DSP ASE includes 8-, 16- and 32-bit SIMD instructions for saturated ...

SAN JOSE, Calif. — MIPS Technologies Inc. is upgrading two of its cores and introducing a new instruction set architecture. The products aim to expand the company's relatively small presence in 32-bit ...

LONDON — MIPS Technologies Inc. and ARC International plc, leading examples of companies that license their intellectual property rather than ship it in their own silicon, are set to make ...

MIPS Technologies has introduced two cores and a 16bit instruction set. The M14K and M14Kc have the same 1.5DMips/MHz performance as the firm’s existing 4K series, with which they share a five-stage ...

Agreement with MIPS Technologies Enables Model Availability to Speed Development of Robust, Optimized MIPS-Based Products SAN JOSE, Calif. and MOUNTAIN VIEW, Calif. – August 18, 2008-- CoWare®, Inc.

Carbon Design Systems, a supplier of tools for the automatic creation, validation, and deployment of virtual hardware models, joined the MIPS Alliance Program (MAP), adding MIPS Technologies to its ...

China-based Loongson has announced two 64-bit quad core processors based around a MIPS-derived architecture and including binary translation to run x86 and ARM code. The nine stage pipelined ...

eWEEK content and product recommendations are editorially independent. We may make money when you click on links to our partners. Learn More. MIPS has had a long, strange trip over the past few ...