New KV cache compaction technique cuts LLM memory 50x without accuracy loss

MIT researchers developed Attention Matching, a KV cache compaction technique that compresses LLM memory by 50x in seconds — ...
EDN

Last-level cache has become a critical SoC design element

LLC, positioned between external memory and internal subsystems, stores frequently accessed data close to compute resources.
Digital Trends

AMD CPUs just got a major performance update for games

X3D Turbo Mode reportedly does a few things to improve performance on 3D V-Cache CPUs. First and most obviously, it limits operations to a single core complex die (CCD). CPUs like the Ryzen 9 7950X3D ...
Electronic Design

Adding Cache to IPs and SoCs

Cache memory significantly reduces time and power consumption for memory access in systems-on-chip. Technologies like AMBA protocols facilitate cache coherence and efficient data management across CPU ...
Neowin

AMD's new patent suggests Ryzen 3D V-cache CPUs may get lot more powerful and faster

AMD recently published a new patent that reveals that the company is working on making its 3D V-cache tech even better. Back in early 2021, we started hearing the first whispers and murmurs of a new ...
Nature

Cache Management and Partitioning in Multicore Systems

Modern multicore systems demand sophisticated strategies to manage shared cache resources. As multiple cores execute diverse workloads concurrently, cache interference can lead to significant ...
EDN

SoC design: When a network-on-chip meets cache coherency

Many people have heard the term cache coherency without fully understanding the considerations in the context of system-on-chip (SoC) devices, especially those using a network-on-chip (NoC). To ...