EDN

The CS4350 PLL DAC Simplifies System Design

Typical Digital to Analog Converters (DACs) require a high-speed Master Clock to clock their digital filters and modulators, as well as some portions of their discrete time analog circuitry. This ...
Electronic Design

How to Design Very Wide Loop BW High-Performance PLL Frequency Synthesizers (Part 2)

This is Part 2 of a three-part series. As discussed in Part 1 and recapped here, modern wireless communications systems (mainly superheterodyne radio transceivers) are now required to deliver higher ...
EDN

Int-N PLL/synthesizer suppresses system noise

The LTC6945 6-GHz integer-N PLL/synthesizer features –226dBc/Hz normalized closed-loop in-band phase noise, –274-dBc/Hz normalized in-band 1/f noise, –157-dBc/Hz wideband phase noise floor, and ...
Electronic Design

Programmable Clock Generator Solves System-Timing Woes

Flexible clock chip tackles design and timing issues by integrating 2 kbits of in-system-programmable EEPROM and 16 kbits of extra EEPROM storage. Timing within all digital and most mixed ...