EDN

Improve top-level simulation strategy for switching DC-DC converters

Just before fabrication, the design flow of all integrated circuits (ICs) culminates in transistor-based, top-level simulations. Unfortunately, verifying functionality, connectivity, and performance ...
EDN

Taking power analysis to the transistor level for a full chip

Almost every chip being taped out today is mixed-signal in nature. In addition to increased integration of analog and RF blocks, designers are using complex power-management techniques to minimize ...
Purdue University

Complete atom-by-atom transistor simulation run in 15 minutes

WEST LAFAYETTE, Ind. - A simulation of electrical current moving through a futuristic electronic transistor has been modeled atom-by-atom in less than 15 minutes by Purdue University researchers. The ...
it.tmcnet

Berkeley Design Announces Fractional-N PLL Transistor-Level Noise Analysis

Berkeley Design Automation has announced the closed-loop noise analysis of fractional-N phase-locked loops (PLLs) at the transistor level. The company is a provider of Precision Circuit Analysis ...
Business Wire

Magma Acquires ACAD, Introduces FineSim Pro Circuit Simulator; Full-Chip, Tri-Mode Circuit Simulator Enables Simulation of Entire Mixed-Signal SoCs at Transistor Level

SANTA CLARA, Calif.--(BUSINESS WIRE)--July 24, 2006--Magma(R) Design Automation Inc. (Nasdaq:LAVA), a provider of semiconductor design software, today announced the availability of FineSim(R) Pro, the ...
Design-Reuse

Cadence Introduces Voltus-Fi Custom Power Integrity Solution, Delivering Foundry-Certified SPICE-Level Accuracy for Transistor-Level Power Signoff

SAN JOSE, Calif. -- Aug 4, 2014 -- Cadence Design Systems, Inc. (NASDAQ: CDNS), a leader in global electronic design innovation, today introduced Cadence® Voltus™-Fi Custom Power Integrity Solution, a ...
Semiconductor Engineering

Using Symbolic Simulation For SRAM Redundancy Repair Verification

Innovations in Very Deep Sub-Micron technologies, such as the advent of three-dimensional FinFET transistor structures, have facilitated the implementation of very large embedded SRAM memories in ...
Semiconductor Engineering

Transistor-Level Verification Returns

Technologies that had become specialist tools are moving back into mainstream usage; shift left is not just about doing things earlier in the flow. A few decades ago, all designers did ...
Design-Reuse

Retargeting IP -> Extraction method verifies IP functions

Keeping pace with the breakneck speed of silicon technology advancement requires substantial manual work. Nowhere is that more apparent than with the reuse of full-, semi- or structured-custom cores.
The Engineer

IBIS Modelling - Part 3: How to Achieve a Quality Level 3 IBIS Model Through Bench Measurement

IBIS models are commonly generated through design circuit simulations. However, there are some cases when the design files are obsolete, unavailable, or only available in an unworkable schematic file ...
Electronic Design

Simulation Vs. Silicon: Avoid Costly Mistakes With Accurate Models

When first-pass silicon arrives back from the foundry, accurate simulation models are critical to first-time success. Of course, we all prefer to avoid expensive learning experiences. So every ...