Semiconductor Engineering

Need For KGD Drives Singulated Die Screening

The move to multi-die packaging is driving chipmakers to develop more cost-effective ways to ensure only known-good die are integrated into packages, because the price of failure is significantly ...
Business Wire

Hprobe Announces New Generation of Magnetic Test Head for Wafer Sort of MRAM in Mass Production

GRENOBLE, France--(BUSINESS WIRE)--Hprobe, a provider of turnkey semiconductor Automatic Test Equipment (ATE) for magnetic devices, today announced a breakthrough magnetic test head revolutionizing ...
Electronic Design

Reducing Logic Device Test Costs

Test-flow partitioning between wafer sort and final package test can have a dramatic impact on the cost of test. In some cases, the migration of package tests can be done over time, but the test ...
Semiconductor Engineering

Using Test And Metrology Data For Dynamic Process Control

Advanced packaging is transforming semiconductor manufacturing into a multi-dimensional challenge, blending 2D front-end wafer fabrication with 2.5D/3D assemblies, high-frequency device ...
EDN

Intel’s ‘casual learning algorithm’ to reduce IC test costs

SANTA CLARA, Calif. – Looking to reduce the soaring costs of IC test, Intel Corp. hopes to leverage its “causal learning algorithm” technology for wafer sorting applications in the fab. Intel is ...
Digi Times

ADLINK high-efficiency die sorting machine solution increases effectiveness of IC packaging and testing

The back-end semiconductor manufacturing process refers to the IC packaging and testing that people often hear about. Specifically, the process known as chip probing (CP) is conducted to test the ...
EDN

Intel’s ‘causal learning algorithm’ to reduce IC test costs

SANTA CLARA, Calif. — Looking to reduce the soaring costs of IC test, Intel Corp. hopes to leverage its “causal learning algorithm” technology for wafer sorting applications in the fab. Intel is ...