EDN

RTL prototyping: a hardware/software co-verification solution

Traditional ASIC and IP verification methods cannot adequately exercise the hardware and software components of today's designs. This is due to tool performance limitations, which impose a bottleneck ...
EDN

Defining the TLM-to-RTL Design Flow

As System-on-Chip (SoC) designs grow ever larger, design and verification flows are changing. A rich mix of features, increased software content, high intellectual property (IP) use and submicron ...
Semiconductor Engineering

Modification Of An Existing E-Graph Based RTL Optimization Tool As A Formal Verification Assistant

A technical paper titled “Datapath Verification via Word-Level E-Graph Rewriting” was published by researchers at Intel Corporation and Imperial College London. “Formal verification of datapath ...
Electronic Design

RTL Design Verification Tool Eliminates Learning Curve

Designed to be easy to use by eliminating the learning curve normally associated with formal register transfer level (RTL) design verification technology, BlackTie is offered as a functional checker ...
Dhaka Tribune

CVES launches course on RTL design, verification and VLSI synthesis

The American International University-Bangladesh (AIUB) inaugurated a new professional industry-focused course titled “RTL Design, Verification, Synthesis and PnR for Digital VLSI Design” on October 5 ...
Semiconductor Engineering

Formal Verification of Security Properties On RTL Designs

A technical paper titled “RTL Verification for Secure Speculation Using Contract Shadow Logic” was published by researchers at Princeton University, MIT CSAIL, and EPFL. “Modern out-of-order ...