Santa Cruz, Calif. – Claiming a new capability for chip designers, startup Bluespec Inc. this week will announce its ability to synthesize SystemVerilog verification assertions into Verilog 1995 RTL ...

The SystemVerilog language standard is one of the hottest topics in EDA today, and with good reason. It takes a huge step up from traditional hardware description languages, incorporating key concepts ...

Design properties can be expressed in OVA, PSL or SystemVerilog languages and used in assertions or cover statements, placed directly in the HDL code of the design or in separate verification blocks.

Adds Support for SystemVerilog Assertions, Flexible Probes, Waveform Generation With Combinational Signals SAN JOSE, CALIF. –– April 13, 2009 –– EVE , the leader in hardware/software ...

Database upgrades, clock-tree and timing debug features, and support for assertion-driven debugging have all been added to Novas' debug systems.