EDN

Synopsys Implementation Solution Included in TSMC 16-nm Reference Flow for FinFET Design

Synopsys, Inc. (Nasdaq: SNPS), a global leader providing software, IP and services used to accelerate innovation in chips and electronic systems, today announced delivery of a comprehensive design ...
Nasdaq

TSMC Certifies Synopsys' Digital and Custom Design Platforms on TSMC 5nm FinFET Process Technology

IC Compiler II and Design Compiler Graphical provide a complete digital implementation flow delivering optimized power, performance, area, and full via pillar support StarRC, PrimeTime, NanoTime, and ...
Nasdaq

Keysight, Synopsys, and Ansys Accelerate RFIC Semiconductor Design with New Reference Flow for TSMC's Most Advanced 4nm RF FinFET Process

New reference flow offers open, efficient radio frequency design solution that supports streamlined migration from previous process nodes Industry-leading electromagnetic simulation tools boost 5G/6G ...
Business Wire

Cadence Digital, Custom/Analog Design Flows Certified and Design IP Available for Intel 16 FinFET Process

SAN JOSE, Calif.--(BUSINESS WIRE)--Cadence Design Systems, Inc. (Nasdaq: CDNS) today announced its digital and custom/analog flows are certified on the Intel 16 FinFET process technology and its ...
Semiconductor Engineering

Self-aligned Fin Cut Last Patterning Scheme for Fin Arrays of 24nm Pitch and Beyond

In 5nm FinFET technology and beyond, SRAM cell size reduction to 6 tracks is required with a fin pitch of 24nm. Fin depopulation is mandatory to enable area scaling ...
Semiconductor Engineering

FinFET Rollout Slower Than Expected

It costs nearly three times more to design a finFET-based chip than a 28nm planar chip, and it takes more than twice as long to get working silicon. The foundry business is heating up as some new and ...