I took these gigabyte figures for NAND and DRAM and turned those into transistors shipped, then doubled the result using that assumption that half of all transistors are memory.

Using just four vertically stacked transistors, they implemented the functionality of a six-transistor 2D NAND with a footprint six times smaller. Arrays of these 3D NAND gates showed outstanding ...

Toshiba announced a flash memory chip that stacks 48 transistors vertically, improving density over previous industry leaders such as Samsung.

Here, the operating principle of an FeFET memory is very similar to that of NAND flash: writing of the memory cell is completed by applying a pulse to the transistor gate, and reading is performed by ...

Accordingly, Intel wants to describe processes in terms of millions of logic transistors per square millimeter, calculated using a 3:2 mix of NAND cells and scan flip flop cells.

The 3D SGVC NAND makes use of arrays of vertically arranged single-gate flat-cell thin film transistors with an ultra thin body, which aren't as sensitive to variation of critical dimensions (CD ...

Porod and his colleagues equipped their new chip with a universal logic gate -- a combination of the NAND and NOR gates. Together, these two logic gates can perform any of the basic arithmetic ...

The NAND flash technology that Toshiba introduced in 1989, making thumb drives, SSDs and your smartphone’s memory possible, has finally reached a development dead end.