Design-Reuse

From Behavioral to RTL Design Flow in SystemC

This paper reports the scientific collaboration between LLR and PROSILOG. The aim of this collaboration was to show the possibility to quickly implement a system into a FPGA, using SystemC 4 as the ...
Semiconductor Engineering

RTL Design-for-Power (DFP) Methodology

Commercial power analysis tools have been available now for over 10 years, operating at the gate and transistor level of abstraction. For analog, mixed-signal, and custom designs, transistor-level ...
Design-Reuse

Method ensures on-track designs

Achieving functional closure on register-transfer-level designs continues to be one of the greatest challenges for today's ASIC and system-on-chip design teams. One facet of that challenge is the goal ...
EDN

Defining the TLM-to-RTL Design Flow

As System-on-Chip (SoC) designs grow ever larger, design and verification flows are changing. A rich mix of features, increased software content, high intellectual property (IP) use and submicron ...
Electronic Design

An Easier Path To RTL For DSP Algorithms

Why are so many designers turning to FPGA implementation for DSP designs? Considering the price/performance ratio for today's high-end FPGAs, not to mention the large numbers of DSP blocks and ...
Semiconductor Engineering

TLM-Driven Design And Verification—Time For A Methodology Shift

While today’s RTL design and verification flows are a step up from the gate-level flows of two decades ago, RTL flows are straining to meet the demands of most product teams. When designs are sourced ...
EDN

Syntax raises abstraction level of RTL design

MUNICH, Germany — Jianwen Zhu, a professor at the University of Toronto, proposed a new register-transfer level (RTL) abstraction syntax which he claimed can be implemented by a modest extension to ...