SystemVerilog was supposed to be such a boon to verification engineers. By providing a Verilog-like language with extensions that made it easy to write transactors, assertions, and checkers, the ...

Efficient and standards compliant modeling for transaction based verification with un-timed test environment modeled in C/C++/SystemC and timed transactors and complex SOC DUT modeled in SystemVerilog ...

Once TestBencher generates VHDL and Verilog test benches, they can be optionally linked to C++ code via the TestBuilder C++ library.