EDN

SpringSoft turns the power of Verdi on SystemVerilog test benches

SystemVerilog was supposed to be such a boon to verification engineers. By providing a Verilog-like language with extensions that made it easy to write transactors, assertions, and checkers, the ...
Electronic Design

Testbench Automation Tool Provides Tight Links To Verilog Simulation

Faster runtime performance, real-time access to built-in Verilog simulation coverage metrics, and a unified graphical environment for waveform analysis are all ...
Electronic Design

Development Environment Supports Mixed C++ And HDL Test Benches

TestBencher Pro v8.0 adds support for mixed C++ and hardware description language (HDL) test benches using the open standard TestBuilder library. This library offers useful verification capabilities, ...
EDN

Spotty support stymies broader acceptance of System Verilog, users say

SAN FRANCISCO — A handful of chip and systems companies said they are seeing real benefits from experiments and limited adoption of System Verilog, mainly in back-end design areas such as verification ...